1. Cross Reference to Related Applications
This application is related to application, Ser. No. 08/897,265, filed on the filing date of this application, ELIMINATION OF RADIUS OF CURVATURE EFFECTS ON P-N JUNCTION AVALANCH BREAKDOWN USING SLOTS, application, Ser. No. 08/897,166, filed on the filing date of this application, entitled USE OF TUNGSTEN FILLED SLOTS AS GROUND PLANE IN INTEGRATED CIRCUIT MANUFACTURE AND ALSO FOR LOW RESISTANCE CONTACT, application, Ser. No. 08/897,167, filed on the filing date of this application, entitled USE OF MULTIPLE SLOTS SURROUNDING BASE REGION OF A BIPOLAR JUNCTION TRANSISTOR TO INCREASE CUMULATIVE BREAKDOWN VOLTAGE and application, Ser. No. 08/897,082, filed on the filing date of this application, entitled USE OF SLOTS IN DEEP ISOLATION AND COLLECTOR PICKUP REGIONS FOR MINIMIZATION OF SUB-COLLECTOR UP-DIFFUSION.
2. Field of the Invention
This invention relates generally to high voltage semiconductor devices. More particularly, this invention relates to high voltage semiconductor devices in which sideways depletion spreading is reduced by utilizing slots.
3. Discussion of the Related Art
The bipolar transistor is an electronic device with two pn junctions in very close proximity. There are three device regions: an emitter region, a base region, and a collector region. The two pn-junctions are known as the emitter-base (EB) junction and the collector-base (CB) junction. Modulation of the current in one pn-junction by means of a change in the bias of the other nearby pn-junction is called bipolar-transistor action. Because the mobility of minority carriers (electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher frequency operation and higher speed performances can be obtained with npn devices. For this reason, the following discussion will be in terms of npn transistors but it is to be understood that the discussion is applicable to pnp transistors as well.
The desired device characteristics of bipolar transistors include: high current gain, high frequency ac operation, fast switching speed, high device-breakdown voltages, minimum device size (to achieve high functional density) and high reliability of device operation. In order for high-frequency ac performance and fast switching speed to be achieved, the parasitic resistances of the transistor; R.sub.E, R.sub.B, and R.sub.C, and the parasitic junction capacitances; C.sub.EB, C.sub.CB, and C.sub.CB must be minimized. In addition, high-level injection effects, for example, the Kirk effect should be avoided. For faithful amplification of ac signals, the Early voltage must be high.
Modern high-speed bipolar junction transistors (BJTs) are generally constrained by the competing concerns of high .beta. (forward current gain) and high base punch-through resistance. Punch-through refers to the effect wherein the neutral base width is reduced to zero at a sufficiently high collector-base voltage, V.sub.cb. With the neutral base reduced to zero, the collector-base depletion region is in direct contact with the emitter-base depletion region. At this point, the collector is effectively short-circuited to the emitter, and as a result a large current flows.
The effects of beta and punch-through voltage are both coupled directly through the base charge, Q.sub.b. The total charge in the base region of a bipolar transistor is given by the product of the doping concentration, N.sub.A, and the base width, W.sub.b. Lowering Q.sub.b raises .beta. but also lowers punch-through voltage at the same time. For the opposite condition, raising Q.sub.b lowers the .beta. but results in a higher punch-through voltage. The trade-off between high .beta. and high punch-though resistance has been a fundamental feature of silicon bipolar junction transistors for many years.
Researchers have attempted to decouple the competing effects of .beta. and punch-through voltage by altering the band gap characteristics of the emitter, the base, or both. lowering the band gap at the base, for instance, by the use of silicon germanium alloys has produced favorable .beta. values with acceptable punch-through voltages. Alternatively, experiments in utilizing silicon carbide alloys to raise the band gap of the emitter region have also produced favorable results. Work is continuing in the semiconductor design field to further increase the performance of these devices by engineering the band gap.
While efforts to engineer the band gap of the emitters and base regions have produced impressive results, these results have not come without certain costs. One of the primary drawbacks of using alloy semiconductors such as silicon germanium or silicon carbide is that forming such allows generally require the use of exotic processing equipment. Typically, heterojunction epitaxial layers are grown using a technique known as molecular beam epitaxy (MBE). In this method the substrate is held in a high vacuum while molecular or atomic beams of the constituent atoms impinge upon its surface. The main problems with MBE machines is that they are characterized by extremely slow growth rates (approximately 1 micron/hour) and are very expensive and very difficult to operate in a manufacturing environment. Moreover, techniques such as MBE for forming heterojunction alloys are generally not compatible with modern processing requirements and structures. In light of these limitations, advanced epitaxial growth techniques like MBE have been limited to research facilities or to specific applications where the level of integration is severely limited and the manufacturing volumes are likewise small. Thus, the goal of simultaneously achieving high .beta. and high punch-through voltage in a bipolar transistor manufactured using conventional silicon processing equipment and techniques has not yet been accomplished.
Another limiting factor in some applications is that there is a requirement for a higher density of devices in a given surface area of the semiconductor chip. In some high-voltage applications, the density is limited by the requirement to provide a sufficiently large depletion zone that necessarily increases as the voltage increases. In junction-isolated SBC transistors, the packing density is relatively low since so much silicon area is taken up by inactive isolation regions. Although the window defining the isolation diffusion may be a minimum size at the surface, the total width of the isolation region there is determined by lateral diffusion. For example, if the epitaxial layer is 12 microns thick and the minimum feature size is 3 microns, the isolation region will approach 24 microns in width (assuming that lateral diffusion is approximately 80% of the vertical diffusion). Thus, the width of the isolation region ends up about twice the thickness of the epitaxial layer in order for the acceptor dopants to penetrate through this layer. In addition, as the operating voltages increase the depletion zone must increase to avoid punch-through or breakdown.
Therefore, what is needed is a semiconductor device that prevents the sideways spreading of the collector-base depletion that preserves a high breakdown voltage.